Nonvolatile semiconductor memory devices, such as a flash memory, capable of electrically writing and erasing are broadly adopted as high-capacity memory media, such as digital cameras, mobile terminals, portable audio apparatuses, and personal computers. Two types of nonvolatile memory cell transistors are known as being used as flash memories: a stacked gate structure type, which includes a floating gate electrode and a control gate electrode; and a charge trap flash structure type (as disclosed in “Multi-Level NAND Flash Memory with 63 nm-node TANOS (Si-Oxide-SiN—Al2O3—TaN) Cell Structure”, IEEE VLSI Tech. Dig. 2006). The charge trap structure is also referred to as a MONOS structure, which is an abbreviation of Metal-Oxide-Nitride-Oxide-Semiconductor.
An active region of an array end in the proximity of a word line (WL) extracting portion is becoming more and more complex in shape, as miniaturization advances. This is because a thin line-and-space pattern should be made such that a lithography margin is secured at an array end where periodicity ends when the pattern is exposed through lithography, since the width of an active region in a cell array portion is becoming more and more miniaturized.
In a MONOS structure, a block insulating film after an element isolation layer such as a shallow trench isolation (STI) is formed, so as to increase an electric field that is applied to a tunnel insulating film during writing and erasing operations and obtain appropriate writing and erasing properties. Thereby, the structure is configured such that a distance between a control gate electrode and a semiconductor substrate is short. In this cell transistor structure, if the STI of the cell array portion become an appropriate depth, the depth of the STI becomes deep at the array end, where the line-and-space pattern is larger than that of the cell array portion. Further, since the control gate electrode and the semiconductor substrate become close to each other, the breakdown voltage deteriorates. That is, the array end may become a portion capable of determining the voltage to be applied to the control gate electrode.
In the stacked gate structure, since an STI adjacent to a floating gate electrode is lowered such that a coupling ratio is maintained as the width of the active region is more shrunk, the distance between a control gate electrode connected to a word line and a semiconductor substrate becomes shorter. Accordingly, if the STI is lowered to a depth appropriate for maintaining the coupling ratio, the depth of the STI becomes deep in the array end where the line-and-space pattern is large, and the semiconductor substrate becomes closer to the control gate electrode than the cell array portion, which results in deterioration in breakdown voltage. Thus, as in the case of the MONOS structure, there is a concern that the array end may become a portion that determines the voltage that can be applied to the control gate electrode.